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PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
Rev. 01 -- 14 October 2002 Product data
1. Description
The PCKEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL, or if positive power supplies are used, PECL input signal. The PCKEL14 is designed to operate in ECL or PECL mode for a voltage supply range of -2.375 V to -3.8 V (or 2.375 V to 3.8 V). The PCKEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor), the SEL pin will select the differential clock input. The common enable (EN) is synchronous, so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled, as can happen with an asynchronous control. The internal flip-flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. The VBB pin (an internally generated voltage supply) is available to this device only. For single-ended conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC-coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.1 mA. When not used, VBB should be left open.
2. Features
s s s s s s s s s s s s 50 ps output-to-output skew at 3.3 V Synchronous enable/disable Multiplexed clock input ESD protection: > 2.5 kV HBM The PCK series contains temperature compensation PECL mode operating range: VCC = 2.375 V to 3.8 V, with VEE = 0 V NECL mode operating range: VCC = 0 V, with VEE = -2.375 V to -3.8 V Internal 75 k pull-down resistors on all inputs, plus a 37.5 k pull-up on CLK Q output will default LOW with inputs open or at VEE Meets or exceeds JEDEC spec EIA/JESD78 IC latch-up test Moisture sensitivity level 1 Flammability rating: UL-94 code V-0 @ 1/8"
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
3. Pinning information
3.1 Pinning
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4
1 2 3 4
20 VCC 19 EN 18 VCC 17 NC
Q0 1 Q0 2 Q1 3
20 VCC 19 EN 18 VCC
PCKEL14PW
Q1 4 Q2 5 Q2 6 Q3 7 Q3 8 Q4 9 Q4 10
17 NC 16 SCLK 15 CLK 14 CLK 13 VBB 12 SEL 11 VEE
PCKEL14D
5 6 7 8 9
16 SCLK 15 CLK 14 CLK 13 VBB 12 SEL 11 VEE
Q4 10
002aaa217
002aaa353
Fig 1. SO20 pin configuration.
Fig 2. TSSOP pin configuration.
3.2 Pin description
Table 1: Symbol Q0-Q4 Q0-Q4 VEE SEL VBB CLK CLK SCLK NC EN VCC Pin description Pin 1, 3, 5, 7, 9 2, 4, 6, 8, 10 11 12 13 14 15 16 17 19 18, 20 Description ECL differential clock outputs, non-inverted ECL differential clock outputs, inverted negative supply voltage ECL clock select input reference voltage output ECL differential clock input, inverted ECL differential clock input, non-inverted ECL scan clock input no connect ECL synchronous enable, Active-LOW positive supply voltage
3.2.1
Power supply connection
CAUTION All VCC and VEE pins must be connected to an appropriate power supply to guarantee proper operation.
MSC895
9397 750 09564
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 October 2002
2 of 15
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
4. Ordering information
Table 2: Ordering information Package Name PCKEL14D PCKEL14PW SO20 TSSOP20 Description plastic small outline package; 20 leads; body width 7.5 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm Version SOT163-1 SOT360-1 Type number
5. Logic diagram
1 2 19
Q0 Q0
EN
Q1 Q1
3 4 Q D
Q2 Q2
5 6
16 15 1
SCLK CLK
Q3 Q3
7 8
0
14
CLK
13 12
VBB SEL
Q4 Q4
9 10
002aaa218
Fig 3. Logic diagram.
CAUTION All VCC and VEE pins must be connected to an appropriate power supply to guarantee proper operation.
MSC895
6. Function table
Table 3: Function table X = Don't care. CLK L H X X X
[1]
9397 750 09564
SCLK X X L H X
SEL L L H H X
EN L L L L H
Q L H L H L[1]
On next negative transition of CLK or SCLK.
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 October 2002
3 of 15
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
7. Limiting values
Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VEE VI Parameter power supply power supply input voltage Conditions PECL mode; VEE = 0 V NECL mode; VCC = 0 V PECL mode; VEE = 0 V; VI VCC NECL mode; VCC = 0 V; VI VEE Io IBB Tamb Tstg Rth(j-a) Rth(j-c) Tsld ESDHBM ESDMM ESCCDM
[1]
Min 0 0 0 0 -0.1 -40 -65
Max 4.1 -4.1 4.1 -4.1 50 100 +0.1 +85 +150 90 60 35 265 >2.50 >100 >1000
Unit V V V V mA mA mA C C C/W C/W C/W C kV V V
output current VBB sink/source ambient temperature storage temperature thermal resistance from junction to ambient thermal resistance from junction to case soldering temperature electrostatic discharge electrostatic discharge electrostatic discharge
continuous surge
0 LFPM 500 LFPM std bd < 2 to 3 sec @ 248 C Human Body Model; 1.5 k; 100 pF Machine Model; 0 k; 200 pF Charge Device Model
30 -
Maximum ratings are those values beyond which device damage may occur.
9397 750 09564
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 October 2002
4 of 15
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
8. Static characteristics
Table 5: PECL DC characteristics[1] VCC = 2.5 V; VEE = 0 V [2] Symbol IEE VOH VOL VIH VIL VBB VIHCMR Parameter power supply current HIGH-level output voltage LOW-level output voltage HIGH-level input voltage output voltage reference HIGH-level input voltage, common mode range (differential) HIGH-level input current LOW-level input current CLK CLK
[1] [2] [3] [4] [5]
[5] [3]
Conditions -
Tamb = -40 C Min Typ 28 Max 40 -
Tamb = +25 C Min Typ 30 Max 40 -
Tamb = +85 C Min Typ 31 Max 42
Unit mA
1325 1460 1620 1435 1545 1620 1475 1545 1620 mV 670 805 945 690 795 880 690 795 880 mV
[3]
single-ended
[4]
1310 690 1.07 1.2 -
1620 1335 1025 690 1.25 2.1 1.15 1.2 -
1620 1335 1025 690 1.25 2.1 1.15 1.2 -
1620 mV 1025 mV 1.31 2.1 V V
LOW-level input voltage single-ended
[4]
IIH IIL
0.5
-
150 -
0.5
-
150 -
0.5
-
150 -
A A A
-300 -
-300 -
-300 -
Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -1.3 V. All loading with 50 to VCC - 2 V. Do not use VBB at VCC < 3.0 V. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
9397 750 09564
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 October 2002
5 of 15
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
Table 6: Positive DC characteristics[1] VCC = 3.3 V; VEE = 0 V [2] Symbol IEE VOH VOL VIH VIL VBB VIHCMR Parameter power supply current HIGH-level output voltage LOW-level output voltage HIGH-level input voltage LOW-level input voltage output voltage reference HIGH-level input voltage, common mode range (differential) HIGH-level input current LOW-level input current CLK others Vp-p < 500 mV Vp-p 500 mV
[4] [3]
Conditions -
Tamb = -40 C Min Typ 32 Max 40 -
Tamb = +25 C Min Typ 32 Max 40 -
Tamb = +85 C Min Typ 34 Max 42
Unit mA
2125 2260 2420 2235 2345 2420 2275 2345 2420 mV 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV 2110 1490 1.87 1.3 1.5 2420 2135 1825 1490 2.05 2.9 2.9 1.95 1.2 1.4 2420 2135 1825 1490 2.05 2.9 2.9 1.95 1.2 1.4 2420 mV 1825 mV 2.11 2.9 2.9 V V V
[3]
single-ended single-ended
IIH IIL
-
-
150 -
-
-
150 -
-
-
150 -
A A A
-300 0.5 -
-300 0.5 -
-300 0.5 -
[1] [2] [3] [4]
Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. Outputs are terminated through a 50 resistor to VCC - 2V. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between Vp-p(min) and 1 V.
9397 750 09564
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 October 2002
6 of 15
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
Table 7: Negative DC characteristics[1] VCC = 0.0 V; VEE = - 3.8 V to -2.375 V[2] Symbol Parameter IEE VOH VOL VIH VIL VBB VIHCMR power supply current HIGH-level output voltage LOW-level output voltage HIGH-level input single-ended voltage LOW-level input voltage output voltage reference HIGH-level input Vp-p < 500 mV voltage, Vp-p 500 mV common mode range (differential) HIGH-level input current LOW-level input current CLK others
[4] [3]
Conditions -
Tamb = -40 C Min Typ 32 Max 40 -
Tamb = +25 C Min Typ 32 Max 40 -880 -
Tamb = +85 C Min Typ 34 Max 42 -880
Unit mA mV
-1175 -1040 -880
-1065 -955
-1025 -955
[3]
-1830 -1695 -1555 -1810 -1705 -1620 -1810 -1705 -1620 mV -1190 -1810 -1.43 -2.0 -1.8 -880 -1165 -880 -1165 -880 mV
single-ended
-1475 -1810 -1.25 -1.35 -0.4 -0.4 -2.1 -1.9 -
-1475 -1810 -1.25 -1.35 -0.4 -0.4 -2.1 -1.9 -
-1475 mV -1.19 V -0.4 -0.4 V V
IIH IIL
-300 0.5
-
150 -
-300 0.5
-
150 -
-300 0.5
-
150 -
A A A
[1] [2] [3] [4]
Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. Outputs are terminated through a 50 resistor to VCC - 2 V. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between Vp-p(min) and 1 V.
9397 750 09564
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 October 2002
7 of 15
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
9. Dynamic characteristics
Table 8: AC characteristics (VCC = 2.375 V to 3.8 V; VEE = 0 V) or (VCC = 0 V; VEE = -2.375 V to -3.8 V) [1] Symbol fmax tPLH Parameter maximum toggle frequency LOW-to-HIGH propagation delay Conditions see Figure 4 CLK to Q (diff); 3.3 V CLK to Q (diff); 2.5 V tPHL tSKEW HIGH-to-LOW propagation delay skew time CLK to Q (SE) SCLK to Q part-to-part within-device; 3.3 V within-device; 2.5 V tJITTER tsu th Vi(p-p) tr/tf cycle-to cycle jitter EN set-up time EN hold time input swing CLK output rise/fall times Q pins (20% - 80%); 3.3 V Q pins (20% - 80%); 2.5 V
[1] [2] [3]
[3] [2]
Tamb = -40 C Min 400 400 330 330 0 0 150 230 Typ >1 0.2 Max 720 800 770 770 200 50 70 <1 1000 500
Tamb = +25 C Min 450 450 350 350 0 0 150 230 Typ >1 680 680 0.2 Max 780 940 830 830 200 50 70 <1 1000 500
Tamb = +85 C Min 475 500 370 370 0 0 150 230 Typ >1 0.2 Max 830 970 880 880 200 50 70 <1 500
Unit GHz ps ps ps ps ps ps ps ps ps ps ps
[2]
1000 mV
230
-
600
230
-
600
230
-
625
ps
VEE can vary 0.3 V. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions. Vi(p-p)(min) is minimum input swing for which AC parameters are guaranteed.
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Product data
Rev. 01 -- 14 October 2002
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Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
900 VO (mVp-p) 800 700 600 500 400 300 200 100 0
002aaa219
Vi(p-p)@150 mV Vi(p-p)@1000 mV
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
FREQUENCY (MHz)
Fig 4. fmax @ 150 mV and 1000 mV input.
10. Application information
Q DRIVER DEVICE Q
D RECEIVER DEVICE D
50
50
VTT
002aaa220
VTT = VCC - 2.0 V.
Fig 5. Typical termination for output driver and device evaluation.
9397 750 09564
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 October 2002
2100
100
200
300
400
500
600
700
800
900
40
9 of 15
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
11. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-05-22 99-12-27
Fig 6. SO20 package outline (SOT163-1).
9397 750 09564 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 October 2002
10 of 15
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c y HE vMA
Z
20
11
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
10
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27
Fig 7. TSSOP20 package outline (SOT360-1).
9397 750 09564 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 October 2002
11 of 15
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
12. Soldering
12.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C small/thin packages.
12.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle
to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
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Product data
Rev. 01 -- 14 October 2002
12 of 15
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
12.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
12.5 Package related soldering information
Table 9: Package[1] BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[4], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable[3] suitable not recommended[4][5] not recommended[6] Reflow[2] suitable suitable suitable suitable suitable
[3]
[4] [5] [6]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
13. Revision history
Table 10: Rev Date 01 20021014 Revision history CPCN Description Product data; initial version (9397 750 09564). Engineering Change Notice 853-2372 2877 (date: 20020909).
9397 750 09564 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 October 2002
13 of 15
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
14. Data sheet status
Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
15. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
16. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
9397 750 09564
Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 October 2002
14 of 15
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
Contents
1 2 3 3.1 3.2 3.2.1 4 5 6 7 8 9 10 11 12 12.1 12.2 12.3 12.4 12.5 13 14 15 16 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Power supply connection . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 12 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 12 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 13 Package related soldering information . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
(c) Koninklijke Philips Electronics N.V. 2002. Printed in the U.S.A
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 14 October 2002 Document order number: 9397 750 09564

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